How to Build a 3:1 Multiplexer Using Two 2:1 Multiplexers
Multiplexers (or muxes) are fundamental building blocks in digital design. They allow a single output line to carry data from one of several input sources, controlled by select lines. While a 2:1 multiplexer can choose between two inputs using a single select bit, many applications require selecting among three or more sources. A common technique is to cascade two 2:1 muxes to create a functional 3:1 multiplexer. This article walks you through the theory, design steps, and practical implementation of a 3:1 mux built from two 2:1 muxes, giving you a clear roadmap for both simulation and hardware realization.
Introduction
In modern digital systems, routing data efficiently is crucial for performance and resource utilization. When a design needs to pick one of three data streams, the simplest hardware solution is often to reuse existing 2:1 multiplexers rather than designing a dedicated 3:1 block. In practice, by strategically connecting two 2:1 muxes, you can achieve the same functionality with minimal extra logic. Think about it: this approach reduces component count, simplifies PCB layout, and can lower power consumption. Below, we explore how to construct a 3:1 multiplexer using two 2:1 multiplexers, covering the underlying logic, step‑by‑step design, and practical tips for implementation.
Understanding the Basic Multiplexers
A 2:1 multiplexer has two data inputs (often called I0 and I1), one select line (S), and a single output (Y). Its Boolean expression is:
Y = (¬S · I0) + (S · I1)
A 3:1 multiplexer expands this concept: it has three data inputs (I0, I1, I2), two select lines (S1, S0), and one output (Y). The select lines form a binary code that chooses which input appears at the output:
| S1 | S0 | Output |
|---|---|---|
| 0 | 0 | I0 |
| 0 | 1 | I1 |
| 1 | 0 | I2 |
| 1 | 1 | — (unused) |
The Boolean equation for a 3:1 mux is:
Y = (¬S1·¬S0·I0) + (¬S1·S0·I1) + (S1·¬S0·I2)
Creating a 3:1 mux from two 2:1 muxes involves splitting the selection into two stages: the first stage chooses between I0 and I1 based on S0, and the second stage selects between the result of the first stage and I2 based on S1.
Design Strategy: Cascading Two 2:1 Muxes
The key insight is to treat the two select bits as a binary decision tree.
- Stage 1 – Use a 2:1 mux with inputs I0 and I1 and select line S0. This yields an intermediate signal M that holds either I0 (when S0 = 0) or I1 (when S0 = 1).
- Stage 2 – Feed M into one input of a second 2:1 mux, and connect I2 to the other input. Use S1 as the select line for this mux. The final output Y will be M when S1 = 0 (i.e., selecting the first‑stage result) or I2 when S1 = 1 (i.e., bypassing the first stage).
This cascade effectively implements the 3:1 truth table because the combination of S1 and S0 uniquely determines which original input reaches the output Turns out it matters..
Step‑by‑Step Implementation
Below is a practical guide to building the circuit using discrete logic gates (e.g., 74HC4051‑style muxes) or integrated multiplexer ICs.
Step 1 – Choose Your 2:1 Mux Components
- Option A: Use two dedicated 2:1 multiplexer ICs (e.g., CD4053, 74HC4051 if configured appropriately).
- Option B: Implement each 2:1 mux with basic gates (AND, OR, NOT) if you need a custom gate‑level design.
Step 2 – Wire the First Stage
I0 ──►│
│► 2:1 MUX (S = S0) ──► M
I1 ──►│
Connect I0 to input A, I1 to input B, and S0 to the select pin of the first mux. Label the output M.
Step 3 – Wire the Second Stage
M ──►│
│► 2:1 MUX (S = S1) ──► Y
I2 ──►│
Feed M into input A of the second mux, I2 into input B, and apply S1 to its select line. The output of this mux is the desired Y.
Step 4 – Verify the Truth Table
| S1 | S0 | I0 | I1 | I2 | Expected Y | Circuit Y | |----|----|----|----|----|----|-----------|-----------| | 0 | 0 | X | X | X | I0 | M = I0 → Y = I0 | | 0 | 1 | X | X | X | I1 | M = I1 → Y = I1 | | 1 | 0 | X | X | X | I2 | M = I0 → Y = I2 | | 1 | 1 | X | X | X | — | M = I1 → Y = I2 |
(“—” indicates the unused combination; the circuit still produces a deterministic output, typically I2.)
Step 5 – Add Control Logic (Optional)
If you need to disable the whole multiplexer, tie an enable pin (available on many mux ICs) to a global enable signal. When the enable is low, the output is forced to a known state (often 0) Simple, but easy to overlook. Took long enough..
Truth Table and Logic Equations
The cascaded design yields the same Boolean expression as a native 3:1 mux. Derivation:
-
First stage:
M = (¬S0·I0) + (S0·I1) -
Second
-
Second stage: The output of the second 2:1 mux is
[ Y = (\overline{S_1}\cdot M) + (S_1 \cdot I_2) ]
Substituting the expression for (M) from the first stage gives
[ \begin{aligned} Y &= \overline{S_1}\big[(\overline{S_0}\cdot I_0) + (S_0 \cdot I_1)\big] + S_1 \cdot I_2 \ &= (\overline{S_1},\overline{S_0}\cdot I_0) + (\overline{S_1},S_0\cdot I_1) + (S_1\cdot I_2) \end{aligned} ]
This sum‑of‑products form exactly matches the canonical truth table of a 3:1 multiplexer:
| S₁ | S₀ | Selected Input | Y |
|---|---|---|---|
| 0 | 0 | I₀ | (\overline{S_1}\overline{S_0}I_0) |
| 0 | 1 | I₁ | (\overline{S_1}S_0I_1) |
| 1 | 0 | I₂ | (S_1I_2) |
| 1 | 1 | I₂ | (S_1I_2) |
Thus the cascade reproduces the desired behavior for all four select combinations; the entry (S_1=1, S_0=1) simply falls through to (I_2), which is harmless and often exploited to reduce wiring when the third select line is permanently tied high Most people skip this — try not to..
Practical Considerations
| Aspect | Cascaded 2:1 MUX Approach | Native 3:1 MUX (if available) |
|---|---|---|
| Component count | Two 2:1 muxes (or equivalent gate packages) | One 3:1 mux |
| Propagation delay | Approximately two mux delays in series (≈ 2 × tₚd) | Single mux delay (≈ tₚd) |
| Power consumption | Slightly higher due to two active stages; still modest for CMOS | Lower, as only one stage switches |
| Layout flexibility | Easy to place each stage where routing congestion is lowest | Requires a larger footprint for the 3‑input select decoder |
| Scalability | Extending to N : 1 simply adds another stage (log₂N muxes) | Requires a wider select decoder or a custom‑width mux |
If the design targets a high‑speed datapath, the extra delay may be mitigated by using faster families (e.g., 74LVC1G157 for the 2:1 muxes) or by implementing the function in a look‑up‑table (LUT) inside an FPGA, where the cascade maps to a single LUT with three address bits.
Alternative Gate‑Level Realization
When only basic logic gates are on hand, the Boolean expression can be drawn directly:
[ Y = \overline{S_1},\overline{S_0},I_0 ;+; \overline{S_1},S_0,I_1 ;+; S_1,I_2 ]
This yields a two‑level AND‑OR network:
- Three 2‑input AND gates (one per product term)
- One 3‑input OR gate (or a cascade of two 2‑input ORs)
Inverters are needed for (\overline{S_0}) and (\overline{S_1}). The gate‑level version is useful in ASIC standard‑cell libraries where a dedicated mux macro may not be available Turns out it matters..
Enable and Power‑Down Handling
Many multiplexer ICs feature an active‑low enable ( (\overline{E}) ) pin. To globally disable the cascaded
