SR flip flop using NOR gate is a fundamental building block in digital electronics that stores a single bit of information by using two cross‑coupled NOR gates. This simple yet powerful circuit forms the basis for more complex sequential logic such as registers, counters, and memory units. Understanding how the NOR‑based SR latch operates helps students grasp the concepts of feedback, bistability, and timing constraints that are essential when designing reliable digital systems.
Introduction
The SR (Set‑Reset) flip flop is the simplest type of bistable multivibrator. When constructed with NOR gates, the circuit exhibits two stable states—set (output Q = 1, (\overline{Q}) = 0) and reset (Q = 0, (\overline{Q}) = 1)—depending on the logic levels applied to its S (Set) and R (Reset) inputs. Think about it: because NOR gates output a logic 0 only when any input is logic 1, the cross‑coupled arrangement forces the outputs to complement each other unless both inputs are simultaneously asserted, which creates an forbidden condition. This article explains the internal operation, truth table, timing considerations, and practical applications of an SR flip flop built exclusively from NOR gates.
Circuit Diagram and Basic Operation
![SR NOR latch diagram] (imaginary placeholder – no external links)
Two NOR gates are cross‑coupled: the output of NOR‑1 feeds one input of NOR‑2, and the output of NOR‑2 feeds one input of NOR‑1. The remaining inputs of each gate are the external S and R signals.
Truth Table
| S (Set) | R (Reset) | Q (next state) | (\overline{Q}) (next state) | Description |
|---|---|---|---|---|
| 0 | 0 | Q (hold) | (\overline{Q}) (hold) | No change – latch retains previous state |
| 0 | 1 | 0 | 1 | Reset – forces Q low |
| 1 | 0 | 1 | 0 | Set – forces Q high |
| 1 | 1 | 0 (invalid) | 0 (invalid) | Forbidden – both outputs low, violates complementarity |
When S = 0 and R = 0, each NOR gate sees at least one input that is the current output of the opposite gate. Because a NOR gate outputs 1 only when all its inputs are 0, the circuit settles into whichever state satisfies the feedback condition, thus holding the previous value Most people skip this — try not to. Nothing fancy..
When S = 1 (regardless of R), the top NOR gate receives a 1 on its S input, forcing its output Q to 0. Still, this 0 is fed back to the bottom NOR gate, which now has both inputs 0 (R and the feedback Q), causing its output (\overline{Q}) to become 1. Here's the thing — the resulting state is Q = 0, (\overline{Q}) = 1, which is the reset condition. Symmetrically, asserting R = 1 forces Q to 1 and (\overline{Q}) to 0 (the set condition) That's the part that actually makes a difference. Worth knowing..
Not obvious, but once you see it — you'll see it everywhere.
If both S and R are driven high simultaneously, each NOR gate sees at least one input = 1, driving both outputs to 0. In practice, this violates the latch’s requirement that Q and (\overline{Q}) be complements, leading to an undefined or metastable condition. In practice, designers avoid this input combination But it adds up..
Scientific Explanation
Bistability and Feedback
A bistable circuit has two stable equilibrium points in its state space. The SR NOR latch achieves this through positive feedback: each gate’s output influences the other gate’s input. Mathematically, the behavior can be captured by the Boolean equations:
[ Q = \overline{S + \overline{Q}} \qquad \overline{Q} = \overline{R + Q} ]
where “+” denotes logical OR and the overbar denotes NOT (the NOR operation). Solving these simultaneous equations yields the four possible operating points listed in the truth table. The two points where S = R = 0 correspond to the stable states; the point S = R = 1 is an unstable equilibrium that collapses to either stable state depending on minute asymmetries or noise.
Timing Characteristics
Propagation delay ((t_{pd})) is the time required for a change at an input to appear at the output. In a NOR‑based SR latch, the total delay from S or R to Q is roughly twice the gate delay because the signal must traverse two NOR gates (S → NOR‑1 → Q, and the feedback path through NOR‑2). Typical TTL NOR gates have a delay of 5–10 ns, giving the latch a response time of 10–20 ns.
Setup and hold times are not strictly defined for a simple latch because it is level‑sensitive; however, when the SR latch is used inside a clocked flip‑flop (e.g., converting to a gated SR or D flip‑flop), the external clock must guarantee that S and R are stable for a short interval before and after the clock edge to avoid racing conditions It's one of those things that adds up..
Metastability
If S and R transition from opposite states to the forbidden (1,1) condition almost simultaneously, the latch may enter a metastable state where Q and (\overline{Q}) linger at an intermediate voltage for an unbounded period. The probability of metastability decreases exponentially with the time allowed for resolution, which is why practical designs insert a small dead‑time or use edge‑triggered master‑slave configurations to forbid simultaneous assertion of S and R.
Steps to Build and Test an SR NOR Latch
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Gather components
- Two 74LS02 (Quad 2‑input NOR) ICs or equivalent discrete NOR gates (e.g., built from MOSFETs).
- Breadboard, power supply (+5 V), ground, and connecting wires.
- Two LEDs with current‑limiting resistors (to monitor Q and (\overline{Q})).
- Two push‑button switches or toggle switches for S and R inputs.
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Wire the circuit
- Connect pin 1 of the first NOR gate to S, pin 2 to the output of the second NOR gate (feedback), and pin 3 to Q (output).
- Connect pin 1 of the second NOR gate to R, pin 2 to the output of the first NOR gate (feedback), and pin 3 to (\overline{Q}).
- Tie the remaining unused inputs of each NOR gate to ground (logic 0) to prevent floating.
- Power VCC to +5 V and GND to ground.
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Verify the hold state
- With both switches open (S = 0, R = 0), observe the LEDs. One should be lit, the other off, indicating the latch retains its previous state. Flip the latch by momentarily pressing S or R and verify that the state changes accordingly.
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Test set and reset
- Press the S switch (S = 1, R = 0) → LED for Q lights, (\overline{Q}) LED off.
- Release S (return to 0,0) → latch holds the set state.
