An SR latch built from NAND gates represents one of the most fundamental building blocks in digital electronics, serving as a basic 1-bit memory element. Unlike its NOR gate counterpart, the NAND-based version operates on active-low logic, meaning the inputs are typically held HIGH and a LOW pulse triggers a state change. Understanding the SR latch NAND gate truth table is essential for anyone studying sequential logic, computer architecture, or embedded systems design, as it reveals how simple logic gates can "remember" a previous state.
Understanding the Circuit Topology
Before diving into the truth table, it helps to visualize the physical arrangement. A NAND-based SR latch consists of two cross-coupled 2-input NAND gates. The output of the first gate feeds into one input of the second gate, and the output of the second gate feeds back into one input of the first gate Simple, but easy to overlook..
The remaining free inputs are designated as S' (Set) and R' (Reset). The apostrophe (or sometimes an overbar) denotes that these are active-low signals. The outputs are Q and Q' (Q-bar), which are always complements of each other during normal operation.
- Gate 1: Inputs are S' and Q'. Output is Q.
- Gate 2: Inputs are R' and Q. Output is Q'.
This cross-coupling creates a feedback loop. It is this loop that allows the circuit to retain information even after the input signals are removed, distinguishing sequential logic from combinational logic Surprisingly effective..
The SR Latch NAND Gate Truth Table
The defining characteristic of the NAND implementation is the active-low input behavior. The following truth table summarizes the next state ($Q_{next}$) based on the current inputs ($S', R'$) and the current state ($Q_{current}$).
| S' (Set) | R' (Reset) | $Q_{next}$ | $Q'_{next}$ | State Name | Description |
|---|---|---|---|---|---|
| 1 | 1 | $Q_{current}$ | $Q'_{current}$ | Hold (Memory) | Inputs inactive; latch retains previous state. Violates $Q = \overline{Q'}$. Active-low Set triggered. |
| 0 | 0 | 1 | 1 | Invalid / Forbidden | Both outputs HIGH. Here's the thing — |
| 0 | 1 | 1 | 0 | Set | $Q$ goes HIGH (1). But |
| 1 | 0 | 0 | 1 | Reset | $Q$ goes LOW (0). That's why active-low Reset triggered. Unpredictable next state. |
Detailed Row Analysis
1. Hold State (S' = 1, R' = 1)
This is the default resting state. Because NAND gates output LOW only when all inputs are HIGH, holding both inputs HIGH allows the feedback loop to dictate the output. If $Q$ was previously 1, Gate 2 sees (1, 1) and outputs 0 ($Q'$). Gate 1 sees (1, 0) and outputs 1 ($Q$). The loop is stable. The same stability applies if $Q$ was previously 0. This is the memory function Took long enough..
2. Set State (S' = 0, R' = 1)
Applying a LOW pulse to S' forces the output of Gate 1 (Q) to HIGH (1), regardless of the other input ($Q'$). Since Q is now 1, and R' is 1, Gate 2 sees two HIGH inputs and drives $Q'$ LOW (0). The latch is now Set ($Q=1$). Even if S' returns to 1, the circuit remains in this state (Hold).
3. Reset State (S' = 1, R' = 0)
Symmetrically, a LOW pulse on R' forces Gate 2 output ($Q'$) to HIGH (1). With $Q'$ HIGH and S' HIGH, Gate 1 outputs LOW (0), driving $Q$ to 0. The latch is Reset ($Q=0$). This state persists after R' returns to HIGH.
4. Invalid / Forbidden State (S' = 0, R' = 0)
This condition must be avoided in standard operation. Driving both inputs LOW forces both NAND gates to output HIGH (1). So naturally, $Q = 1$ and $Q' = 1$. This breaks the fundamental rule that $Q$ and $Q'$ must be complements. The real danger occurs when the inputs transition from (0,0) to (1,1) simultaneously. Both gates attempt to enter the Hold state, but the feedback signals are racing. The final state depends on proprietary transistor switching speeds and wire delays (a race condition), making the result non-deterministic But it adds up..
Comparison: NAND vs. NOR Implementation
It is crucial to distinguish the NAND latch from the NOR latch, as confusing the two is a common source of errors in digital design exams and practical debugging.
| Feature | NAND Gate SR Latch | NOR Gate SR Latch |
|---|---|---|
| Input Polarity | Active Low (S', R') | Active High (S, R) |
| Hold Condition | S' = 1, R' = 1 | S = 0, R = 0 |
| Set Condition | S' = 0, R' = 1 | S = 1, R = 0 |
| Reset Condition | S' = 1, R' = 0 | S = 0, R = 1 |
| Invalid Condition | S' = 0, R' = 0 | S = 1, R = 1 |
| Default Input State | HIGH (Pulled Up) | LOW (Pulled Down) |
Key Takeaway: For a NAND latch, you "pull the trigger" by pulling the line LOW. For a NOR latch, you trigger by pulling the line HIGH.
Timing Considerations and Propagation Delay
The truth table describes static behavior, but real circuits operate in time. When an input pulse arrives, the output does not change instantaneously Which is the point..
- Propagation Delay ($t_{pd}$): The time required for a change at S' or R' to reflect at Q and Q'. Since the signal must propagate through two gates in the feedback loop to fully stabilize, the total settling time is roughly $2 \times t_{pd}$ per gate.
- Pulse Width: The Set or Reset pulse must be held LOW long enough for the signal to propagate through the loop and lock the state. A pulse shorter than the total propagation delay may fail to flip the latch (a "runt pulse").
- Setup and Hold Times: While typically discussed in clocked flip-flops, the concept applies here regarding the stability of inputs before and after the triggering edge.
Practical Applications and Debouncing
One of the most classic real-world applications of the SR latch NAND gate truth table logic is mechanical switch debouncing.
Mechanical switches (push buttons, toggles) suffer from "contact bounce"—the metal contacts physically vibrate for milliseconds when opening or closing, generating multiple rapid HIGH/LOW transitions. A microcontroller reading this directly would register multiple presses Simple, but easy to overlook. Practical, not theoretical..
A NAND SR latch solves this perfectly:
- Connect the switch between Ground (LOW) and the S' input (with a pull-up resistor to Vcc).
- When the switch moves to "Set," it pulls S' LOW. * Connect the switch's other throw to the R' input. The latch sets Q=1.
