A truth table for a NAND gate lists every possible input combination and shows that the output is LOW only when every input is HIGH. For every other combination, the output is HIGH. This simple relationship makes the NAND gate one of the most important building blocks in digital electronics and Boolean logic Not complicated — just consistent..
What Is a NAND Gate?
A NAND gate is a digital logic gate that performs an AND operation followed by a NOT operation. Because of that, the name NAND comes from “NOT AND. ” If an AND gate produces a HIGH output only when all of its inputs are HIGH, a NAND gate produces the opposite result But it adds up..
In a standard two-input NAND gate:
- Input
Aand inputBcan each be0or1. - The output
Yis1unless both inputs are1. - Under the positive-logic convention,
1represents HIGH and0represents LOW.
The NAND operation is commonly written as:
[ Y = \overline{A \cdot B} ]
This can also be expressed as:
[ Y = A \text{ NAND } B ]
The overline means that the result of A · B is inverted Simple, but easy to overlook. Simple as that..
Truth Table for a Two-Input NAND Gate
| Input A | Input B | Output Y |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The final row is the only case in which the output is 0. This happens because both inputs are 1, causing the internal AND operation to produce 1; the NAND gate then inverts that result to 0.
A useful way to remember the table is:
A NAND output is LOW only when all inputs are HIGH.
How to Read the NAND Truth Table
Each row represents one complete input state. A two-input gate has two possible values for each input, so it has:
[ 2^2 = 4 ]
possible combinations.
- Row 1:
0 NAND 0 = 1 - Row 2:
0 NAND 1 = 1 - Row 3:
1 NAND 0 = 1 - Row 4:
1 NAND 1 = 0
Changing either input from 1 to 0 immediately changes the NAND output from 0 to 1. This behavior is useful in control circuits because one LOW input can disable a condition that would otherwise produce a LOW output.
NAND Compared with AND
A NAND gate is the logical complement of an AND gate. Their outputs are opposite for every input combination.
| A | B | AND Output | NAND Output |
|---|---|---|---|
| 0 | 0 | 0 | 1 |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 |
This relationship can be written as:
[
