Nand Gate SR Latch Truth Table: A Complete Guide
The nand gate sr latch truth table is a fundamental reference for anyone studying digital electronics. On top of that, it outlines how a simple cross‑coupled NAND gate configuration can store a binary state, providing the Set (S) and Reset (R) inputs with corresponding outputs Q and (\overline{Q}). Understanding this truth table helps designers predict latch behavior, troubleshoot circuits, and lay the groundwork for more complex sequential logic.
This changes depending on context. Keep that in mind.
Understanding the NAND Gate SR Latch
The Basic NAND Gate
A NAND gate is a universal logic element whose output is low only when all inputs are high. In Boolean terms, the output is (\overline{A \cdot B}). This property makes NAND gates ideal for building memory elements because they can be interconnected to form feedback loops that retain a state.
What Is an SR Latch?
An SR latch is a bistable multivibrator that has two inputs: Set (S) and Reset (R). Also, the latch holds its state when both inputs are de‑asserted. When S is activated, the latch sets its output Q to high (logic 1); when R is activated, Q is reset to low (logic 0). The term latch implies that the circuit remembers the input condition without a clock signal.
The Truth Table of a Nand Gate SR Latch
Below is the canonical nand gate sr latch truth table. It lists every possible combination of S and R and the resulting outputs Q and (\overline{Q}).
| S (Set) | R (Reset) | Q (Output) | (\overline{Q}) (Complement) |
|---|---|---|---|
| 0 | 0 | Invalid | Invalid (race condition) |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | Hold | Hold (no change) |
Key points highlighted in bold:
- S = 0, R = 0 is an illegal condition because both NAND gates receive a low signal simultaneously, forcing Q and (\overline{Q}) to fight for dominance. This creates a race condition that must be avoided in proper circuit design.
- S = 0, R = 1 forces the latch into the Set state (Q = 0, (\overline{Q}) = 1). Note that the output Q is low when the latch is set in a NAND‑based implementation; this is a common source of confusion.
- S = 1, R = 0 forces the latch into the Reset state (Q = 1, (\overline{Q}) = 0).
- S = 1, R = 1 leaves the latch unchanged, preserving its current state (the Hold condition).
How to Derive the Truth Table – Step‑by‑Step
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Draw the Circuit
Connect two NAND gates in a cross‑coupled configuration. The output of each gate feeds back to the opposite gate’s input. The external S input connects to the first NAND gate’s non‑inverting input, and R connects to the second NAND gate’s non‑inverting input. -
Identify Input Conditions
List all possible combinations of S and R (four cases). Remember that each input can be either 0 (low) or 1 (high) Worth keeping that in mind. Still holds up.. -
Analyze Each Case
- For S = 0, R = 0: Both NAND gates receive a low on one input, causing their outputs to go high. This forces the feedback inputs to be high, which paradoxically drives both outputs to the same state, violating the complementary nature of Q and (\overline{Q}). Hence, the condition is undefined.
- For S = 0, R = 1: The first NAND gate’s output becomes high (because one input is low), feeding a low signal to the second gate’s feedback input, making its output low. So naturally, Q = 0 and (\overline{Q}) = 1.
- For S = 1, R = 0: Symmetrically, the second NAND gate’s output goes high, forcing the first gate’s output low, resulting in Q = 1 and (\overline{Q}) = 0.
- For S = 1, R = 1: No external low signals are present; both gates receive only feedback inputs. Their outputs remain unchanged, so Q and (\overline{Q}) retain their prior values.
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Summarize the Results
Populate the truth table with the findings from step 3. The table above reflects this systematic derivation.
Scientific Explanation Behind the Truth Table
Set and Reset Dynamics
- Set (S = 0): Activates the first NAND gate, causing its output to become high. This high signal is fed back to the second gate, forcing its output low. The low output of the second gate is the Set result (Q = 0). In a NAND‑based latch, low equals set because the latch is active‑low.
- Reset (R = 0): Mirrors the set operation but on the opposite gate. The second NAND gate’s output goes high, driving the first gate’s output
